A Designer s Guide to Built-in Self-Test by Charles E. Stroud

By Charles E. Stroud

A up to date technological enhance is the artwork of designing circuits to check themselves, known as a integrated Self-Test (BIST). This notion used to be first proposed round 1980 and has grown to develop into one of many most crucial checking out ideas on the present time, in addition to for the long run. This e-book is written from a designer's viewpoint and describes the key BIST techniques which have been proposed and carried out on account that 1980, besides their merits and boundaries. The BIST techniques contain the integrated common sense Block Observer, pseudo-exhaustive BIST innovations, round BIST, scan-based BIST, BIST for normal constructions, BIST for FPGAs and CPLDs, mixed-signal BIST, and the combination of BIST with concurrent fault detection suggestions for online checking out. specific awareness is paid to system-level use of BIST so as to maximize the advantages of BIST via lowered checking out time and value in addition to excessive diagnostic answer. the writer spent 15 years as a clothier at Bell Labs the place he designed over 20 construction VLSI units and three creation circuit forums. 16 of the VLSI units contained BIST of varied forms for normal constructions and basic sequential common sense, together with the first BIST for Random entry stories (RAMs), the 1st thoroughly self-testing built-in circuit, and the 1st BIST for mixed-signal structures at Bell Labs. He has spent the previous 10 years in academia the place his study and improvement keeps to target BIST, together with the first BIST for FPGAs and CPLDs in addition to persisted paintings within the quarter of BIST for basic sequential common sense and mixed-signal structures. He holds 10 US patents (with five extra pending) for numerous different types of BIST techniques. consequently, the writer brings a distinct mixture of data and adventure to this sensible consultant for designers, attempt engineers, product engineers, procedure diagnosticians, and bosses.

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Therefore, the voltage at the output node, would be given by where represents the equivalent resistance of the conducting PFETs (from the output node to and represents the equivalent resistance of the conducting NFETs (from the output node to Depending on the ratio of these resistances along with the switching threshold(s) of the gate(s) being driven by the output of this faulty gate, the output voltage of the faulty gate may or may not be interpreted as an incorrect logic value such that the fault may or may not be detected at a primary output.

Fault Models, Detection, and Simulation 27 Chapter 2. Fault Models, Detection, and Simulation only one fault in each group of equivalent faults needs to be emulated; this helps to reduce fault simulation time by reducing the number of faults to be emulated. A stuck-at-1 fault at any input of an OR (NOR) gate is equivalent to the output stuck-at1 (stuck-at-0). In the case of an inverter (buffer), the input stuck-at-0 is equivalent to the output stuck-at-1 (stuck-at-0) while the input stuck-at-1 is equivalent to the output stuck-at-0 (stuck-at-1).

However, there are other factors that influence the fault coverage calculation. These include undetectable and potentially detected faults, both of which can lower the overall fault coverage that be obtained for most circuits unless one specifically considers these types of faults and how to deal with them in the fault coverage calculation. As we saw in the case of the gate-level fault model, the individual elementary logic gates are completely and easily testable. Therefore, it is the way in which we interconnect these gates that leads to testability and testing problems.

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